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surface mount rf pin switch diodes technical data features ? unique configurations in surface mount packages C add flexibility C save board space C reduce cost ? switching C low capacitance C low resistance at low current ? low failure in time (fit) rate [1] ? matched diodes for consistent performance ? better thermal conductivity for higher power dissipation ? lead-free option available note: 1. for more information see the surface mount pin reliability data sheet. hsmp-389x series hsmp-489x series description/applications the hsmp-389x series is optimized for switching applica- tions where low resistance at low current and low capacitance are required. the hsmp-489x series products feature ultra low parasitic inductance. these products are specifically designed for use at frequencies which are much higher than the upper limit for conventional pin diodes. gux 1 2 3 6 5 4 notes: 1. package marking provides orientation, identification, and date code. 2. see electrical specifications for appropriate package marking. pin connections and package marking
2 package lead code identification, sot-23/143 (top view) package lead code identification, sot-323 (top view) package lead code identification, sot-363 (top view) absolute maximum ratings [1] t c = +25 c symbol parameter unit sot-23/143 sot-323/363 i f forward current (1 s pulse) amp 1 1 p iv peak inverse voltage v 100 100 t j junction temperature c 150 150 t stg storage temperature c -65 to 150 -65 to 150 jc thermal resistance [2] c/w 500 150 notes: 1. operation in excess of any one of these conditions may result in permanent damage to the device. 2. t c = +25 c, where t c is defined to be the temperature at the package pins where contact is made to the circuit board. esd warning: handling precautions should be taken to avoid static discharge. common cathode #4 common anode #3 series #2 single #0 unconnected pair #5 dual anode 4890 common cathode f common anode e series c single b dual anode 489b series shunt pair low inductance single t unconnected trio l 123 654 123 654 123 654 u high frequency series v 123 654 dual switch model r 123 654
3 electrical specifications, t c = 25 c, each diode package minimum maximum maximum part number marking lead breakdown series resistance total capacitance hsmp- code code configuration voltage v br (v) r s ( ? )c t (pf) 3890 g0 [1] 0 single 100 2.5 0.30 3892 g2 [1] 2 series 3893 g3 [1] 3 common anode 3894 g4 [1] 4 common cathode 3895 g5 [1] 5 unconnected pair 389b g0 [2] b single 389c g2 [2] c series 389e g3 [2] e common anode 389f g4 [2] f common cathode 389l gl [2] l unconnected trio 389r s [2] r dual switch mode 389t z [2] t low inductance single 389u gu [2] u series-shunt pair 389v gv [2] v high frequency series pair test conditions v r = v br i f = 5 ma v r = 5 v measure f = 100 mhz f = 1 mhz i r 10 a notes: 1. package marking code is white. 2. package is laser marked. high frequency (low inductance, 500 mhz C 3 ghz) pin diodes minimum maximum typical maximum typical part package breakdown series total total total number marking voltage resistance capacitance capacitance inductance hsmp- code [1] configuration v br (v) r s ( ? )c t (pf) c t (pf) l t (nh) 489x ga dual anode 100 2.5 0.33 0.375 1.0 test conditions v r = v br i f = 5 ma f = 1 mhz v r = 5 v f = 500 mhz C measure v r = 5 v f = 1 mhz 3 ghz i r 10 a note: 1. sot-23 package marking code is white; sot-323 is laser marked. typical parameters at t c = 25 c part number series resistance carrier lifetime total capacitance hsmp- r s ( ? ) (ns) c t (pf) 389x 3.8 200 0.20 @ 5 v test conditions i f = 1 ma i f = 10 ma f = 100 mhz i r = 6 ma
4 hsmp-389x series typical performance, t c = 25 c, each diode typical applications for multiple diode products figure 1. total rf resistance at 25 c vs. forward bias current. 100 10 1 0.1 rf resistance (ohms) i f forward bias current (ma) 0.01 0.1 1 10 100 120 115 110 105 100 95 90 85 11030 i f forward bias current (ma) figure 3. 2nd harmonic input intercept point vs. forward bias current. input intercept point (dbm) diode mounted as a series attenuator in a 50 ohm microstrip and tested at 123 mhz 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 04 8121620 v r reverse voltage (v) total capacitance (pf) 1 mhz 1 ghz figure 2. capacitance vs. reverse voltage. 200 160 120 80 40 0 10 20 15 25 30 t rr reverse recovery time (ns) forward current (ma) figure 4. typical reverse recovery time vs. reverse voltage. v r = 2v v r = 5v v r = 10v 100 10 1 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 i f forward current (ma) v f forward voltage (v) figure 5. forward current vs. forward voltage. 125 c 25 c 50 c 1 1 2 3 4 0 56 b1 b2 b3 2 3 1 11 rf in rf out 2 2 3 456 1 0 0 2 +v v on off figure 6. hsmp-389l used in a sp3t switch. figure 7. hsmp-389l unconnected trio used in a dual voltage, high isolation switch.
5 typical applications for multiple diode products (continued) figure 11. hsmp-389v series/shunt pair used in a 1.8 ghz transmit/receive switch. figure 10. hsmp-389u series/shunt pair used in a 900 mhz transmit/receive switch. figure 8. hsmp-389l unconnected trio used in a positive voltage, high isolation switch. figure 9. hsmp-389t used in a low inductance shunt mounted switch. rf in rf out 1 +v 0 2 0 +v on off 4 5 6 1 11 2 2 3 rf in rf out 4 5 6 12 3 4 rcvr xmtr bias ant pa bias hsmp-389u lna 4 rcvr bias xmtr hsmp-389v antenna 4 4 rcvr xmtr bias ant cc
6 typical applications for multiple diode products (continued) rf common rf common rf 1 bias 1 bias bias rf 2 bias 2 figure 12. simple spdt switch, using only positive current. rf common rf 1 rf 2 bias figure 14. switch using both positive and negative bias current. figure 15. very high isolation spdt switch, dual bias. figure 13. high isolation spdt switch, dual bias. rf 2 rf 1 rf common rf 2 rf 1 bias
7 equivalent circuit model hsmp-389x chip* 0.12 pf* * measured at -20 v 0.5 ? r j r s c j r j = 20 ? i 0.9 r t = 0.5 + r j c t = c p + c j i = forward bias current in ma * see an1124 for package models typical applications for hsmp-489x low inductance series microstrip series connection for hsmp-489x series in order to take full advantage of the low inductance of the hsmp-489x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in figure 17. 12 3 hsmp-489x figure 16. internal connections. figure 17. circuit layout. microstrip shunt connections for hsmp-489x series in figure 18, the center conductor of the microstrip line is inter- rupted and leads 1 and 2 of the hsmp-489x diode are placed across the resulting gap. this forces the 1.5 nh lead inductance of leads 1 and 2 to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. the 0.3 nh of shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.032" thick material. 50 ohm microstrip lines pad connected to ground by two via holes figure 18. circuit layout. 0.3 nh 0.3 nh 0.3 pf 1.5 nh 1.5 nh figure 19. equivalent circuit. co-planar waveguide shunt connection for hsmp-489x series co-planar waveguide, with ground on the top side of the printed circuit board, is shown in figure 20. since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. co-planar waveguide groundplane center conductor groundplane figure 20. circuit layout. 0.3 pf 0.75 nh figure 21. equivalent circuit. a spice model is not available for pin diodes as spice does not provide for a key pin diode characteristic, carrier lifetime.
8 assembly information 0.026 0.075 0.016 0.035 figure 22. pcb pad layout, sot-363. (dimensions in inches). 0.026 0.035 0.07 0.016 figure 23. pcb pad layout, sot-323. (dimensions in inches). 0.037 0.95 0.037 0.95 0.079 2.0 0.031 0.8 dimensions in inches mm 0.035 0.9 figure 24. pcb pad layout, sot-23. dimensions in inches mm 0.075 1.9 0.071 1.8 0.112 2.85 0.079 2 0.033 0.85 0.041 1.05 0.108 2.75 0.033 0.85 0.047 1.2 0.031 0.8 0.033 0.85 figure 25. pcb pad layout, sot-143. time (seconds) t max temperature ( c) 0 0 50 100 150 200 250 60 preheat zone cool down zone reflow zone 120 180 240 300 figure 26. surface mount assembly profile. smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot package, will reach solder reflow temperatures faster than those with a greater mass. agilent s diodes have been qualified to the time-temperature profile shown in figure 26. this profile is representative of an ir reflow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporat- ing solvents from the solder paste. the reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. the rates of change of tempera- ture for the ramp-up and cool- down zones are chosen to be low enough to not cause deformation of the board or damage to compo- nents due to thermal shock. the maximum temperature in the reflow zone (t max ) should not exceed 235 c. these parameters are typical for a surface mount assembly process for agilent diodes. as a general guideline, the circuit board and components should be exposed only to the minimum tempera- tures and times necessary to achieve a uniform reflow of solder.
9 package characteristics lead material .................... copper (sot-323/363); alloy 42 (sot-23/143) lead finish............................................................................ tin-lead 85-15% maximum soldering temperature .............................. 260 c for 5 seconds minimum lead strength .......................................................... 2 pounds pull typical package inductance .................................................................. 2 nh typical package capacitance .............................. 0.08 pf (opposite leads) package dimensions outline 23 (sot-23) outline 143 (sot-143) 3 1 2 side view top view end view dimensions are in millimeters ( inches ) 1.02 (0.040) 0.89 (0.035) 0.60 (0.024) 0.45 (0.018) 1.40 (0.055) 1.20 (0.047) 2.65 (0.104) 2.10 (0.083) 3.06 (0.120) 2.80 (0.110) 2.04 (0.080) 1.78 (0.070) 1.02 (0.041) 0.85 (0.033) 0.152 (0.006) 0.066 (0.003) 0.10 (0.004) 0.013 (0.0005) 0.69 (0.027) 0.45 (0.018) 0.54 (0.021) 0.37 (0.015) x x x package marking code (xx) date code (x) 0.69 (0.027) 0.45 (0.018) 1.40 (0.055) 1.20 (0.047) 2.65 (0.104) 2.10 (0.083) 0.60 (0.024) 0.45 (0.018) 0.54 (0.021) 0.37 (0.015) 0.10 (0.004) 0.013 (0.0005) 1.04 (0.041) 0.85 (0.033) 0.92 (0.036) 0.78 (0.031) 2.04 (0.080) 1.78 (0.070) dimensions are in millimeters (inches) 0.15 (0.006) 0.09 (0.003) 3.06 (0.120) 2.80 (0.110) package marking code (xx) 43 1 2 x x x date code (x) outline sot-363 (sc-70 6 lead) outline sot-323 (sc-70 3 lead) 2.20 (0.087) 2.00 (0.079) 1.35 (0.053) 1.15 (0.045) 1.30 (0.051) ref. 0.650 bsc (0.025) 2.20 (0.087) 1.80 (0.071) 0.10 (0.004) 0.00 (0.00) 0.25 (0.010) 0.15 (0.006) 1.00 (0.039) 0.80 (0.031) 0.20 (0.008) 0.10 (0.004) 0.30 (0.012) 0.10 (0.004) 0.30 ref. 10 0.425 (0.017) typ. dimensions are in millimeters ( inches ) package marking code (xx) x x x date code (x) 2.20 (0.087) 2.00 (0.079) 1.35 (0.053) 1.15 (0.045) 1.30 (0.051) ref. 0.650 bsc (0.025) 2.20 (0.087) 1.80 (0.071) 0.10 (0.004) 0.00 (0.00) 0.25 (0.010) 0.15 (0.006) 1.00 (0.039) 0.80 (0.031) 0.20 (0.008) 0.10 (0.004) 0.30 (0.012) 0.10 (0.004) 0.30 ref. 10 0.425 (0.017) typ. dimensions are in millimeters ( inches ) package marking code (xx) x x x date code (x)
10 ordering information specify part number followed by option. for example: h smp - 389x - xxx bulk or tape and reel option part number; x = lead code surface mount pin option descriptions -blk = bulk, 100 pcs. per antistatic bag -tr1 = tape and reel, 3000 devices per 7" reel -tr2 = tape and reel, 10,000 devices per 13" reel tape and reeling conforms to electronic industries rs-481, taping of surface mounted components for automated placement. for lead-free option, the part number will have the character "g" at the end, eg. -tr2g for a 10k pc lead-free reel. device orientation user feed direction cover tape carrier tape reel for outline sot-143 note: "ab" represents package marking code. "c" re p resents date code. end vie w 8 mm 4 mm top view abc abc abc abc for outlines sot-23, -323 note: "ab" represents package marking code. "c" represents date code. end vie w 8 mm 4 mm top view abc abc abc abc end vie w 8 mm 4 mm top view note: "ab" represents package marking code. "c" represents date code. abc abc abc abc for outline sot-363
11 tape dimensions and product orientation for outline sot-23 9 max a 0 p p 0 d p 2 e f w d 1 ko 8 max b 0 13.5 max t1 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.15 0.10 2.77 0.10 1.22 0.10 4.00 0.10 1.00 + 0.05 0.124 0.004 0.109 0.004 0.048 0.004 0.157 0.004 0.039 0.002 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 ? 0.10 0.229 0.013 0.315 + 0.012 ? 0.004 0.009 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance between centerline w f e p 2 p 0 d p d 1 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.19 0.10 2.80 0.10 1.31 0.10 4.00 0.10 1.00 + 0.25 0.126 0.004 0.110 0.004 0.052 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 ? 0.10 0.254 0.013 0.315+ 0.012 ? 0.004 0.0100 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance a 0 9 max 9 max t 1 b 0 k 0 for outline sot-143
www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (65) 6756 2394 india, australia, new zealand: (65) 6755 1939 japan: (+81 3) 3335-8152(domestic/international), or 0120-61-1280(domestic only) korea: (65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (65) 6755 2044 taiwan: (65) 6755 1843 data subject to change. copyright ? 2004 agilent technologies, inc. obsoletes 5968-7701e ma rch 24 , 2004 5989-0486en tape dimensions and product orientation for outlines sot-323, -363 p p 0 p 2 f w c d 1 d e a 0 an t 1 (carrier tape thickness) t t (cover tape thickness) an b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.25 0.094 0.004 0.094 0.004 0.047 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.061 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 0.30 0.254 0.02 0.315 0.012 0.0100 0.0008 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance for sot-323 (sc70-3 lead) an 8 c max for sot-363 (sc70-6 lead) 10 c max angle width tape thickness c t t 5.4 0.10 0.062 0.001 0.205 0.004 0.0025 0.00004 cover tape

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